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 Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
PT2318
DESCRIPTION
PT2318 is a sound fader controller IC utilizing CMOS Technology specially designed for car radio hi-fi audio applications. Four selectable stereo inputs, 1 mono input, bass, treble, volume, balance and fader controls, mute function and a special loudness feature which is automatically controlled in combination with the volume level setting are all built into a single I2C bus controlled stereo preamplifier chip having the highest performance and reliability. Pin assignments and application circuits are optimized for easy PCB layout and cost saving advantages.
FEATURES
* * * * * * * * * * * * CMOS technology I2C bus control interface 4 selectable stereo inputs 1 mono input Volume, Balance and Fader controls Bass & Treble controls Noise reduction circuit interface provided External equalizer interface provided Mute control at audio signal zero crossing Internal power-on reset function Mute function controlled via the I2C bus or pin Special automatic loudness feature in combination with the volume setting
APPLICATIONS
* Car audio * Hi-Fi audio applications
PT2318 V1.2
-1-
March, 2006
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Sound Fader Controller IC
PT2318
LOUD_L BAS1_L BAS2_L
BLOCK DIAGRAM
VOL1_L SEL_L TRE_L MUTE
Mute Function Z ero Cross Detector Left Channel Volume 1 Loudness Left Channel Bass Control Left Channel Treble Control Volume 2 Balance Fader Rear FL_OU T Volume 2 Balance Fader F ront SL_O UT
VREF VCC G ND CAP
IN _L1 IN _L2 IN _L3 IN_L4 MON O IN_R1 IN_R2 IN _R3 IN _R4 Input Source Selector R ight C hannel Volume 1 Loudness Right Channel Bass Control R ight Channel Treble Control Logic
I C Bus
2
SCL SDA
Volume 2 Balance Fader F ront
FR _OUT
Volume 2 Balance Fader Rear
SR_O UT
LOUD_R
BAS1_R
PT2318 V1.2
VOL1_R
-2-
BAS2_R
TRE_R
SEL_R
March, 2006
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Sound Fader Controller IC
PT2318
PIN CONFIGURATION
SDA GND SL_OUT FL_OUT TRE_L BAS2_L BAS1_L VOL1_L LOUD_L SEL_I IN_L4 MUTE IN_L3 MONO IN_L2 IN_L1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26
SCL VCC SR_OUT FR_OUT TRE_R BAS2_R BAS1_R VOL1_R LOUD_R SEL_R IN_R4 VREF IN_R3 CAP IN_R2 IN_R1
P T 23 1 8
25 24 23 22 21 20 19 18 17
PT2318 V1.2
-3-
March, 2006
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Sound Fader Controller IC
PT2318
Pin No. 1 2 3 4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN DESCRIPTION
Pin Name SDA GND SL_OUT FL_OUT
TRE_L BAS2_L BAS1_L VOL1_L LOUD_L SEL_L IN_L4 MUTE IN_L3 MONO IN_L2 IN_L1 IN_R1 IN_R2 CAP IN_R3 VREF IN_R4 SEL_R LOUD_R VOL1_R BAS1_R BAS2_R TRE_R FR_OUT SR_OUT VCC SCL
I/O I O O
I/O I/O I I I O I I I I I I I I I I O I I I I/O I/O O O I
Description Serial Data Input Pin Ground Left Rear Channel Output Pin Left Front Channel Output Pin Left Channel Treble Control Pin or may be used as External Equalizer Input Pin Left Channel Bass Control Pin or may be used as External Equalizer Output Pin Left Channel Bass Control Pin Left Control Section Volume Input Pin Left Control Section Loudness Input Pin Left Channel Output Source Selector Left Channel Source 4 Input Pin Mute Function Control Pin Left Channel Source 3 Input Pin Input "MONO" Source Left Channel Source 2 Input Pin Left Channel Source 1 Input Pin Right Channel Source 1 Input Pin Right Channel Source 2 Input Pin Supply Electronic Filtering Right Channel Source 3 Input Pin Reference Voltage (0.5Vcc) Right Channel Source 4 Input Pin Right Channel Output Source Selector Right Control Section Loudness Input Pin Right Control Section Volume 1 Input Pin Right Channel Bass Control Pin Right Channel Bass Control Pin Or may be used as External Equalizer Output Pin Right Channel Treble Control Pin Or may be used as External Equalizer Input Pin Right Front Output Pin Right Rear Output Pin Supply Voltage Serial Clock Input Pin
PT2318 V1.2
-4-
March, 2006
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Sound Fader Controller IC
PT2318
FUNCTION DESCRIPTION
BUS INTERFACE
Data are transmitted to and from the microprocessor to the PT2318 via the SDA and SCL. The SDA and SCL make up the BUS Interface. It should be noted that the pull-up resistors must be connected to the positive supply voltage.
DATA VALIDITY
A data on the SDA Line is considered valid and stable only when the SCL Signal is in HIGH State. The HIGH and LOW States of the SDA Line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL D a t a Lin e S ta b le , D a t a Va lid D a ta C h a ng e A llo w e d
START AND STOP CONDITIONS
A Start Condition is activated when 1. the SCL is set to HIGH and 2. SDA shifts from HIGH to LOW State. The Stop Condition is activated when 1. SCL is set to HIGH and 2. SDA shifts from LOW to HIGH State. Please refer to the timing diagram below.
SC L
SD A
S t a rt
Sto p
PT2318 V1.2
-5-
March, 2006
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Sound Fader Controller IC
PT2318
BYTE FORMAT
Every byte transmitted to the SDA Line consists of 8 bits. Each byte must be followed by an Acknowledge Bit. The MSB is transmitted first.
ACKNOWLEDGE
During the Acknowledge Clock Pulse, the master (P) puts a resistive HIGH level on the SDA Line. The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during the Acknowledge Clock Pulse so that the SDA Line is in a Stable Low State during this Clock Pulse. Please refer to the diagram below.
CLK 1 2 3 4 7 8 9
DATA Start
MSB A cknowledgment from R eceiver
The audio processor that has been addressed has to generate an Acknowledge after receiving each byte, otherwise, the SDA Line will remain at the High Level during the ninth (9th) Clock Pulse. In this case, the master transmitter can generate the STOP Information in order to abort the transfer.
TRANSMISSION WITHOUT ACKNOWLEDGE
If you want to avoid the acknowledge detection of the audio processor, a simpler P transmission may be used. Wait one clock and do not check the slave acknowledge of this same clock then send the new data. If you use this approach, there are greater chances of faulty operation as well as decrease in noise immunity.
PT2318 V1.2
-6-
March, 2006
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Sound Fader Controller IC
PT2318
INTERFACE PROTOCOL
The interface protocol consists of the following: 1. START Condition 2. Chip Address Byte=80H 3. ACK=Acknowledge Bit 4. Data Byte 5. STOP Condition Please refer to the diagram below:
MSB First Byte LSB
START
10001000 Chip Address
Subaddress
ACK
Data Byte
ACK
STOP
Notes: 1. ACK=ACKNOWLEDGE 2. Max. Clock Speed=100K Bits/S The SUBADDRESS is the Second Byte transmitted following the CHIP ADDRESS Byte. Please refer to the table below.
MSB 7 0 0 0 0 0 0 0 0
6 0 0 0 0 0 0 0 0
5 0 0 0 0 0 0 0 0
4 0 0 0 0 0 0 0 0
3 0 0 0 0 0 0 0 0
2* 0 0 0 0 1 1 1 1
LSB 1* 0* 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1
Function
Volume/Loudness Fader: Front, Right Fader: Front, Left Fader: Rear, Right Fader: Rear, Left Bass Treble Selector Switch
Note: These are Significant SUBADDRESS bits. The last bits of SUBADDRESS are named "specific bit". When more than one data bit send to PT2318, the SUBADDRESS will increase automatically depend on specific bit. It is unnecessary to send to SUBADDRESS, data bit will fill in SUBADDRESS bit. Please refer to following table.
START Start Data Data Data Data Sub Chip ACK ACK ACK ACK ACK Byte Byte Byte Byte Address Address 80H 00H Corresp Corresp Corresp Correspo onding onding onding nding Sub Sub Sub Sub Address Address Address Address 00H 01H 02H 03H ACK STOP End
PT2318 V1.2
-7-
March, 2006
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Sound Fader Controller IC
PT2318
The Third Byte following the CIP ADDRESS & SUBADDRESS is defined in the table below. MSB LSB Function 7 6 5 4 3 2 1 0 ZCM LOFF X X X X X X GMU X X X X X X X V5 FFR5 FFL5 FSR5 FSL5 X X X V4 FFR4 FFL4 FSR4 FSL4 BAS4 TRE4 X V3 FFR3 FFL3 FSR3 FSL3 BAS3 TRE3 X V2 FFR2 FFL2 FSR2 FSL2 BAS2 TRE2 SC2 V1 FFR1 FFL1 FSR1 FSL1 BAS1 TRE1 SC1 V0 FFR0 FFL0 FSR0 FSL0 BAS0 TRE0 SC0 Volume/Loudness Fader: Front, Right Fader: Front, Left Fader: Rear, Right Fader: Rear, Left Bass Treble Selector Switch
X=Irrelevant (It should be noted that during testing, this bit is given the value of "1")
I2C BUS START-UP TIMING
After Power is turned ON, PT2318 needs to wait for a short time in order to insure stability. This waiting period is relative to the value of Cref. When Cref=10 F, the waiting time period for PT2318 to send I2C Bus Signal is at least 300ms. If the waiting time period is less than 300ms, I2C Control may fail. Please refer to the figure below.
V
POWER ON 90% VDD
VDD at least 300ms
SDA/SCL
PT2318 V1.2
-8-
March, 2006
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Sound Fader Controller IC
PT2318
SOURCE SELECTOR
PT2318 provides 4 selectable stereo inputs and one mono input. The source selector is used to select any one of the mentioned source input options. Please refer to the table below.
Input Source
Stereo Inputs: IN_L1 & IN_R1 Stereo Inputs: IN_L2 & IN_R2 Stereo Inputs: IN_L3 & IN_R3 Stereo Inputs: IN_L4 & IN_R4 Mono Input: MONO Notes: 1. SC0 to SC2=Source Selector Control Bits 2. X=Irrelevant
Source Selector Bits SC2 SC1 SC0 1 1 1 1 1 0 1 0 1 1 0 0 0 X X
PT2318 V1.2
-9-
March, 2006
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Sound Fader Controller IC
PT2318
VOLUME CONTROL
The Volume Control Function consists of two blocks; namely, Volume 1 Control Block and Volume 2 Control Block.
VOLUME 1 CONTROL BLOCK
The Volume 1 Control Block has an attenuation range of +20dB to -31dB at 1dB/step. The left and right channels have the same gain/attenuation setting. This block operates in conjunction with the Loudness Control. When the Volume 1 Control maximum gain (=20dB) is selected, the filter characteristic is linear. The filter characteristic increases automatically over a range of 32dB down to a setting of -12dB. This means that the Volume 1 Control Block maximum filter characteristics is obtained at a -12dB setting. If the volume is further reduced, the filter characteristics are not in any way affected. The maximum selected filter characteristics is determined by the external components. Please refer to the diagram below.
Volume control and Loudness (Low Roll-Off Frequency included)
VOLUME 2 CONTROL BLOCK
The Volume 2 Control Block operates in combination with the Balance and Fader Functions. Each output has one independent attenuator which has a control range of 0dB to -55dB at 1dB/step with an additional mute step.
PT2318 V1.2
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March, 2006
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Sound Fader Controller IC
PT2318
BASS FUNCTION
The bass function has a control range of -15dB to +15dB at 40Hz. The basic step width of the bass control is 3dB. The intermediate steps are obtained by switching 1.5dB boost and 1.5 dB attenuation steps. The bass control function can be disabled via the I2C Bus. If the bass control function is disabled, the internal signal flow is discontinued, and the pins -- BAS2_L and BAS2-R are used as inputs for connecting an external equalizer. The Bass Function Frequency Response curve is shown below:
TREBLE FUNCTION
The Treble Function has a control range of -12dB to +12dB at 1.5dB / step at 15KHz. The basic step width of the treble control is 3dB and the intermediate steps are obtained by switching 1.5dB boost and 1.5 dB attenuation steps. The treble control function can be disabled via the I2C Bus. If the treble control function is disabled, the internal signal flow is discontinued, and the treble pins -- TRE_L and TRE_R -- are used as inputs for connecting an external equalizer. The Treble Function Frequency Response Curve is given below.
PT2318 V1.2
- 11 -
March, 2006
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Sound Fader Controller IC
PT2318
VOLUME SETTING
The volume setting table is given below. The loudness characteristic increases in a linear manner for every step in the volume whose range is from +20dB to -11dB.
GV (dB) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11
V5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
V4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
V3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
V2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
PT2318 V1.2
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Sound Fader Controller IC
The loudness characteristic is constant during the volume range from -12dB to -31 dB.
PT2318
V4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 V3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 V2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 V1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 V0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GV (dB) -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31
V5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
The steps are repeated for range -28dB to -31dB.
GV(dB) -28 -29 -30 -31 -28 -29 -30 -31 -28 -29 -30 -31
V5 0 0 0 0 0 0 0 0 0 0 0 0
V4 0 0 0 0 0 0 0 0 0 0 0 0
V3 1 1 1 1 0 0 0 0 0 0 0 0
V2 0 0 0 0 1 1 1 1 0 0 0 0
V1 1 1 0 0 1 1 0 0 1 1 0 0
V0 1 0 1 0 1 0 1 0 1 0 1 0
PT2318 V1.2
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March, 2006
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Sound Fader Controller IC
The Volume 2 (Balance & Fader) Setting is shown below.
PT2318
FSR3 FSR3 FFL3 FFR3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 FSR2 FSR2 FFL2 FFR2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FSR1 FSR1 FFL1 FFR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 FSR0 FSR0 FFL0 FFR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GV (dB)
0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35
FSR5 FSR5 FFL5 FFR5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
FSR4 FSR4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
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Sound Fader Controller IC
FSR5 FSR5 FFL5 FFR5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSR4 FSR4 FFL4 FFR4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSR3 FSR3 FFL3 FFR3 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 FSR2 FSR2 FFL2 FFR2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 FSR1 FSR1 FFL1 FFR1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
PT2318
FSR0 FSR0 FFL0 FFR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GV (dB)
-36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 MUTE MUTE MUTE MUTE MUTE MUTE MUTE MUTE
Note: Only the subaddress changes, the data remains the same for a particular range.
PT2318 V1.2
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Sound Fader Controller IC
Bass setting is shown below.
PT2318
BAS3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BAS2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 BAS1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 BAS0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GBASS (dB) +15.0 +13.5 +15.0 +13.5 +15.0 +13.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0 (see note 1) 0 (see note 2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 -13.5 -15.0 -13.5 -15.0 (see note 3) (see note 3) (see note 3) (see note 3 & 4)
BAS4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Notes: 1. Recommended Data Word for step 0dB. 2. Result of 1.5dB boost and 1.5dB attenuation. 3. The last four bass control data words mute the bass response. 4. The last bass and treble control data words (00000) enable the external equalizer connection.
PT2318 V1.2
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March, 2006
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Sound Fader Controller IC
Treble setting is shown below.
PT2318
TRE3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 TRE2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 TRE1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 TRE0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
GTREBLE (dB) +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +12.0 +10.5 +9.0 +7.5 +6.0 +4.5 +3.0 +1.5 0 (see note 1) 0 (see note 2) -1.5 -3.0 -4.5 -6.0 -7.5 -9.0 -10.5 -12.0 (see note 3) (see note 3) (see note 3) (see note 3) (see note 3) (see note 3) (see note 3) (see note 3 & 4)
TRE4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Notes: 1. Recommended Data Word for step 0dB. 2. Result of 1.5dB boost and 1.5dB attenuation. 3. The last eight treble control data words select the treble output. 4. The last bass and treble control data words (00000) enable the external equalizer connection.
PT2318 V1.2
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March, 2006
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Sound Fader Controller IC
PT2318
MUTE
PT2318 provides three mute modes namely: 1. Zero Crossing Mode via the I2C bus using 2 independent zero crossing detectors. 2. Fast Mute via Mute Pin 3. Fast Mute via I2C Bus either by General Mute (GMU) or by Volume 2 Block Setting. The following table shows the setting for the Zero Crossing Mode and the General Mute Mode
GMU 0 0 1 1
ZCM 0 1 0 1
Function Direct MUTE off MUTE off delayed until the next Zero Crossing Direct MUTE MUTE delayed until the next Zero Crossing
Notes: 1. GMU=General Mute Bit (Mute control for all outputs) 2. ZCM=Zero Crossing Mode Bit The mute function is immediately performed if the ZCM="0". If ZCM="1", the mute is activated after changing the GMU bit. The actual mute switching is delayed until the next zero crossing of the audio frequency signal. The left and right audio channels are independent of each other, therefore, there are two built-in comparators controlling the independent mute switches. In order to avoid too much delay in mute switching when very low frequencies are processed, the maximum delay time is limited to a typical value of 100ms by an integrated timing circuit and an external capacitor. This timing circuit is triggered by the reception of a new data word for the switch function (including a GMU bit). After an external capacitor is discharged and charged, the muting switch follows the GMU bit if there was no zero crossing detected during that particular time. Externally controlling the mute function is possible. If the mute pin is set to Ground, all outputs are muted immediately (this is the hardware mute.). Please refer to the diagram below.
PT2318
12 MUTE
HARDWARE MUTE SWITCH
The mute request overwrites all mute controls via the I2C bus for the time the pin is held at "LOW" level. The hardware mute function is ideal for Radio Data System applications. The zero crossing mute avoids modulation plops. This feature is advantageous when the changing presets and/or sources.
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Sound Fader Controller IC
PT2318
INPUT SIGNAL SELECTION VIA ZERO CROSS MUTE MODE
A selection from the Input A (IN_L1) to Input B (IN_L2) Left Channels produces a modulation click at the time of the switching. This will depend on the difference between the signal values. Please refer to the diagram below for the zero cross function (L Channel Only)
V 4 ( 1) 3 2 1 0 t1 -1 -2 -3 -4 ( 3) t2 ( 2) t
Notes: 1. (1)=Output 2. (2)=Input 2 (IN_L2) 3. (3)=Input 1 (IN_L1) At t1, the maximum different between signals is 7Vp-p. At this point, a loud click can be heard. Using the zero cross detector, no modulation click is audible.
LOUDNESS FUNCTION
The Loudness Function is used in combination with Volume 1 Control Block and may be enabled or disabled via the I2C Bus Control. Please refer to the table below for Loudness Function setting.
Loudness Function Loudness On Loudness Off
Note: LOFF=Loudness Function Control Bit
LOFF 0 1
PT2318 V1.2
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Sound Fader Controller IC
PT2318
Symbol Vcc Topr Tstg
Vpin
ABSOLUTE MAXIMUM RATING
Parameter Supply voltage Operating temperature Storage temperature Voltage at each pin (when Pin 2 as GND) Conditions Min. 0 -40 -65
0
Max. 10 +85 +150
Vcc
Unit V
V
ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Vcc=8.5V, Rs=600, RL=10k, CL=2.5nF, AC Coupled, f=1KHz, Ta=25, Gain Control: Gv=0dB, Bass=Linear, Treble=Linear, Fader=Off, Balance in Mid Position Loudness Off)
Parameter Supply voltage Supply current Internal DC voltage (Input & Output) Max. voltage gain Input sensitivity Symbol Vcc Ic VDC GVmax Rs=0, RL= Vi (rms) VO-2000mV, Gv=20dB CKIN=220nF, CKVL=220nF, Zi=Zi(min) Low frequency (-1dB) CKIN=220nF, CKVL=220nF, Zi=Zi(min) Low frequency (-3dB) fro CKIN=220nF, CKVL=220nF, Zi=Zi(min) High frequency (-1dB) CKIN=470nF, CKVL=220nF, Zi=Zi(typ) Low frequency (-3dB) cs THD RR S/N ct Zi Vi=2V, 250Hz to 10KHz 20Hz to 12.5KHz, Vi=100mV, Gv=20dB 20Hz to 12.5KHz, Vi=1V, Gv=0dB 20Hz to 12.5KHz, Vi=2V, Gv=0dB 20Hz to 12.5KHz, Vi=2V, Gv=-10dB Vr(rms)<200mV, f=100Hz Vo=2.0V, Gv=0dB Vo=2.0V, Gv=12dB Vo=2.0V, Gv=12dB Between bus input & signal outputs Conditions Min. 7.5 3.75 19 60 30 20000 17 90 22 Typ. 8.5 26 4.0 20 200 96 0.07 0.05 0.2 0.03 62 99 91 83 110 30 Max. 9.5 32 4.25 21 40 Unit V mA V dB mV Hz Hz Hz Hz dB % % % % dB dB dB dB dB K
Roll-off frequency
Channel separation Total harmonic distortion Ripple rejection Signal to noise ratio Crosstalk Input impedance
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Sound Fader Controller IC
Parameter Input isolation Symbol f=1KHz s f=12.5KHz 95 2.7 2.3 130 0 150 30 130 2.4 120 25 13 13 106 86 1 100 51 1 15 4 Conditions Min. Typ. 104
PT2318
Max. 220 200 40 220 220 50 22 1.0 2 3 2 +20 Unit dB dB V V K dB K K K V V V V V dB dB dB dB dB dB dB dB dB dB dB dB dB
(One selected source to any other input)
Max. input voltage THD<0.5%, Vcc=8.5V Vi (rms) (RMS value) THD<0.5%, Vcc=7.5V Output impedance Zo Output load RL 10 resistance Voltage gain Gv (Source selector) Control Section (Source Selector not connected, Source Resistance=600) Volume input 70 Input impedance Zi Loudness input 20 Output impedance Zo Output load RL 2 resistance Max. input voltage Vi(rms) THD<0.5% Gv=20dB Noise output Gv=0dB Vno voltage Gv=-66dB MUTE position Total continuous control range CRtot Recommended control range Step range Step resolution Gstep Step error between any adjoining step Gv=+20 to -50dB Ga Attenuation set error Gv=-51 to -66dB Gt Gain tracking error Gv=+20 to -50dB Mute attenuation MUTEatt 95 Volume 1 Control + Loudness Continuous volume CRvol control range Voltage gain Gv -31 Step resolution Gstep f=40Hz Max. loudness LBmax f=10KHz -
PT2318 V1.2
- 21 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
Parameter Symbol Bass Control Max. boost Gbass (Bass control) Max. attenuation Step resolution Gstep (Toggle switching) Step error between any Gstep adjoining step Treble Control Max. boost Gtreble Max. attenuation Gtreble Max. boost 2 Gtreble Step resolution Gstep (Toggle switching) Step error between any Gstep adjoining step Volume 2 + Balance + Fader Controls Continuous attenuation CR (Fader & volume control) Step resolution Gstep Attenuation set error Gstep Hardware Mute Mute: Active Input level VSWLOW Zero Crossing Mute Discharger current Id Charge current Ich Delay switch level VSWDEL Delay time td Window for audio signal Vwind zero crossing detection Muting at Power Supply Drop Supply drop for MUTE Vccdrop active I2C Bus Control High level input voltage VIH Low level input voltage VIL Conditions f=40Hz f=40Hz f=40Hz f=40Hz f=15KHz f=15KHz f>15KHz f=15KHz f=15KHz Min. +14 -14 +11 -11 Typ. +15 -15 1.5 +12 -12 1.5 55 1 -
PT2318
Max. +16 -16 1 +13 -13 15 1 2 2 Unit dB dB dB dB dB dB dB dB dB dB dB dB
-300 6.9 3.4 -0.3
0.8 0.6 -150 1.5 100 50 7 -
9.5 +1.5
V A A V ms mV V V V
Cm=10nF
PT2318 V1.2
- 22 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
PT2318
APPLICATION CIRCUIT
I C Bus
2
MCU
1 2 3
SDA GND SL_OUT FL_OUT TRE_L BAS2_L BAS1_L VOL1_L LOUD_L SEL_l IN_L4
SCL 32 VCC 31 SR_OUT 30 FR_OUT 29 TRE_R 28 BAS2_R 27 BAS1_R 26 VOL1_R 25 LOUD_R 24 SEL_R 23 IN_R4 22 VREF 21 IN_R3 20 CAP 19 IN_R2 18 IN_R1 17 + 47 F + 100 F 150nF 5.6nF 33nF CKVL 220nF 2.2K 8.2nF 20K
To Output 5.6nF 33nF CKVL 220nF 2.2K 20K 8.2nF 150nF
4 5 6 7 8 9 10 11
To Output
PT2318
Input Source 4 (Left Channel) Mute Input Source 3 (Left Channel) Mono Source Input Input Source 2 (Left Channel) Input Source 1 (Left Channel)
Input Source 4 (Right Channel) Input Source 3(Right Channel) Input Source 2 (Right Channel) Input Source 1 (Right Channel)
10nF
12 MUTE 13
IN_L3 MONO IN_L2 IN_L1
15 16
CKIN
PT2318 V1.2
- 23 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
PT2318
Package Type 32 Pins, SOP, 300mil 32 Pins, DIP, 600mil Top Code PT2318-S PT2318
ORDER INFORMATION
Valid Part Number PT2318-S PT2318
PT2318 V1.2
- 24 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
PT2318
PACKAGE INFORMATION
32 PINS, SOP, 300MIL
PT2318 V1.2
- 25 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
Symbols A A1 A2 b b1 b2 c c1 D E e H L Min. 0.004 0.082 0.014 0.014 0.026 0.007 0.007 0.812 0.292
0.405 0.021 0
PT2318
Nom. 0.088 0.016 0.016 0.028 0.008 0.008 0.818 0.296 0.050 BSC. 0.412 0.031 4
Max. 0.104 0.30 0.094 0.020 0.018 0.032 0.0125 0.010 0.824 0.299
0.419 0.041 8
Notes: 1. Dimensioning and tolerancing per ANSI Y14.5-1982. 2. Dimension D does not include mold flash, protrusions or gate burrs. Mold Flash, protrusion or gate burrs shall not exceed 0.15mm (0.006 in) per side. 3. Dimension E does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. The chamfer on the body is optional. It is not present, a visual index feature must be located within the crosshatched area. 5. L is the length of the terminal for soldering to a substrate. 6. The lead width B as measured 0.36 mm (0.014 in) or greater above the seating plane, shall not exceed a maximum value of 0.61 mm (0.24 in) 7. Controlling dimension: MILLIMETER. 8. N=Number of terminal position (N=32) 9. Refer to JEDEC MO-119 variation AC. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2318 V1.2
- 26 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
PT2318
32 PINS, DIP, 600MIL
PT2318 V1.2
- 27 -
March, 2006
Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.princeton.com.tw
Sound Fader Controller IC
Symbol A A1 B B1 C D E E1 e1 eA L Q S Min. 0.170 0.015 0.016 0.045 0.009 1.600 0.600 0.530
0.120 0 0.065 0.065
PT2318
Nom. 0.100 BSC. 0.600 BSC. Max. 0.200 0.050 0.022 0.067 0.015 1.670 0.625 0.560
0.150 15 0.080 0.087
Notes: 1. Refer to applicable symbol list. 2. Dimension and tolerancing per ANSI Y14.5-1982 3. applies to spread leads prior to installation. 4. N=Number of terminal position (N=32) 5. D & E1 does not include mold flash. Allowable flash is 0.010 per side. 6. Outlines on which the seating plane is coincident with the base plane (A1=0) terminal lead standoffs are not required, and B1 may equal B along any part of the lead above the seating/base plane. 7. Pin 1 identifier must be located in this area. 8. Controlling dimension: INCH. 9. Refer to JEDEC MO-015 variation AP. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.
PT2318 V1.2
- 28 -
March, 2006


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